The Content Addressable Memory (CAM) comprises three major kinds of cell structures today. These three CAM cell structures include two key VM-based (volatile) CAM cells and one NVM-based (Non-volatile) CAM cell. The VM-based CAM cell includes the DRAM-based CAM and the SRAM-based CAM cells, while the NVM-based CAM cell includes the NAND-based CAM and NOR-based CAM cells. There were many prior art of SRAM-based CAM cells and DRAM-based CAM cells.
Up to date, the SRAM-based CAM cell greatly outperforms the DRAM-based CAM cell and dominates the VM-based CAM market. It is because no power-hungry refresh cycle is needed in any SRAM-based CAM cell design.
There were few NVM-based CAM cells proposed until a NAND-based CAM cell structure was presented in U.S. Pat. No. 8,169,808, entitled “NAND FLASH CONTENT ADDRESSABLE MEMORY.”
Apart from two traditional functions of “Read and Write” of the regular memories such as DRAM, SRAM, EEPROM, NOR and NAND, a CAM cell has the third additional function of “Compare.”
In normal Read operation of regular memory, the plurality of input pins are applied with the address bits and then memory will respond it by outputting the corresponding addressed Byte or Word data within Tacc time, depending on x8 or x16 configuration of the addressed memory.
By contrast, in CAM memory's normal Compare operation, the plurality of input pins are applied with the data bits and then CAM memory will perform Compare or Search function and then respond to it by outputting the corresponding address within the Tacc time if a match is found. If more than a single match has occurred, then an on-chip priority encoder will decide and output the right address of the matched data.
So far, the DRAM-based CAM has been gradually phased out in market place due to its disadvantageous need for its constant refresh-cycle that consumes too much power and is prone to data loss. Conversely, the SRAM-based CAM does not require the refresh cycle to sustain its stored data but it suffers disadvantages of the big cell size and the risk of losing the VM stored data once the VDD power is removed.
Unlike the above mentioned the VM-based CAM cells, DRAM-based CAM cell and the SRAM-based CAM cell, Micron's NAND-based CAM cell is NVM-based CAM cell that has the advantages of small cell size and zero risk of losing data when VDD power is shut off. But the disadvantage of the NAND-based CAM cell is the slow 20 μs Compare speed. The typical speed difference between DRAM-based and SRAM-based CAM cells is less than 100 ns.
Traditionally, there are two types of CAM cells such as BCAM and TCAM. The BCAM cell stands for the Binary CAM cell that stores two logic states such as “1” and “0”, while the TCAM cell stands for Ternary CAM cell that stores three logic states such as “1”, “0” and “X”. The “X” stands for the “Don't-care” state.
But Ternary CAM cell is never equal to BCAM cell in terms of number of transistors in all prior arts of DRAM-based CAM cell, SRAM-based CAM cell and NAND-based CAM cell. Typically, each TCAM cell size is much larger than each BCAM cell size because TCAM needs to add extra devices to add the third “X” logic state. One exemplary SRAM-based TCAM cell comprises sixteen (16) transistors, while the SRAM-based BCOM cell comprises ten (10) transistors.
Both VM-based BCAM or TCAM cells are taking too much silicon area because it comprises two circuit parts. The first circuit part is a “Latch” to store the CAM's bit data and the second circuit part is a “Comparator”, which is used to perform Compare function.
By contrast, the NVM-based BCAM or TCAM cells take much smaller silicon area because it combines both functions of “Latch” and “Compare” into one die due to its non-volatile storage characteristics. But NVM NAND-based BCAM cannot be easily converted into NAND-based TCAM because the inherent cell string limitation.
In light of the above pros and cons of CAMs of prior art, the present invention of the preferred NOR-based CAM cell and array is aimed at solving the above cons and disadvantages.